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IDT5V2305 2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER
INDUSTRIAL TEMPERATURE RANGE
2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER
FEATURES: DESCRIPTION:
IDT5V2305
* High performance 1:5 clock driver for general purpose applications * Operates up to 170MHz at VDD = 2.5V * Operates up to 200MHz at VDD = 3.3V * Pin-to-pin skew < 50ps * VDD range: 2.3V to 3.6V * Output enable glitch suppression * 25 on-chip series dampening resistors * Available in TSSOP and VFQFPN packages
The IDT5V2305 is a high performance, low skew clock buffer that operates up to 200MHz. One bank of five outputs provides low skew copies of CLK. Through the use of control pin G, the outputs of bank Y(0:4) can be placed in a low state regardless of CLK input. The device operates in 2.5V and 3.3V environments. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals. The IDT5V2305 is characterized for operation from -40C to +85C.
FUNCTIONAL BLOCK DIAGRAM
3
G
9
CONTROL LOGIC
Y0
25
5 25 16
Y1
CLK
6 25
Y2
11 25
Y3
13 25
Y4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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c 2003 Integrated Device Technology, Inc.
SEPTEMBER 2003
DSC 6177/11
IDT5V2305 2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
CLK
GND VDD Y0 GND Y1 Y2 VDD GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CLK
VDD
1
VDD VDD Y4 GND Y3 VDD G
16 15 14 GND 13 12 11 10 VDD NC Y4 NC Y3 NC
VDD Y0 NC Y1 Y2 VDD
2 3 4 5 6 7 8 9
G
VDD
TSSOP TOP VIEW
VFQFPN TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDD VI VO IIK IOK IO TSTG Description Power Supply Voltage Input Voltage(2) Output Voltage(2) Input Clamp Current VI < 0 or VI > VDD Output Clamp Current VO < 0 or VO > VDD Continuous Total Output Current VO < 0 to VDD Storage Temperature Max -0.5 to +4.6 -0.5 to VDD +0.5 -0.5 to VDD +0.5 Unit V V V mA mA mA
CAPACITANCE(TA = +25C, f = 1MHz, VIN = 0V)
Parameter CIN Description Input Capacitance VI = 0V or VDD Min. -- Typ. 2.5 Max. -- Unit pF
50 50 50
-65 to +150
FUNCTION TABLE(1)
Inputs G CLK X H L H
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care
Output Y(0:4) L H
C
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Not to exceed 4.6V.
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IDT5V2305 2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
TERMINAL Symbol I/O G I Y(0:4) CLK GND VDD O I PWR Description Output Enable Control for Y(0:4) Outputs. This output enable is active HIGH. If this pin is Logic HIGH, the Y(0:4) clock outputs will follow the input clock (CLK). If this pin is logic LOW, the Y(0:4) outputs will drive low independent of the state of CLK. Buffered Output Clocks Input Reference Frequency Ground DC Power Supply, 2.3V to 3.6V
RECOMMENDED OPERATING RANGE
Symbol VDD VIL VIH VI IOH IOL TA Description Internal Power Supply Voltage Input Voltage LOW Input Voltage HIGH Input Voltage Output Current HIGH Output Current LOW Ambient Operating Temperature VDD = 3V to 3.6V VDD = 2.3V to 2.7V VDD = 3V to 3.6V VDD = 2.3V to 2.7V VDD = 3V to 3.6V VDD = 2.3V to 2.7V VDD = 3V to 3.6V VDD = 2.3V to 2.7V -40 Min. 2.3 Typ. 2.5 3.3 Max. 3.6 0.8 0.7 Unit V V V VDD -12 -6 12 6 +85 V mA mA C
2 1.7 0
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol VIK IIN IDD Parameter Input Voltage Input Current Static Device Current(1) Test Conditions VDD = 3V, IIN = -18mA VI = 0V or VDD CLK = 0V or VDD, IO = 0mA, VDD = 3.3V Min. Typ. Max - 1.2 5 25 Unit V A A
NOTE: 1. For IDD over frequency, see TEST CIRCUIT AND WAVEFORMS.
DC ELECTRICAL CHARACTERISTICS - VDD = 3.3V 0.3V
Symbol VOH Parameter HIGH level Output Voltage Test Conditions IOH = -100A VDD = Min. to Max. VDD = 3V IOH = -12mA IOH = -6mA IOH = 100A VDD = Min. to Max. VDD = 3V IOH = 12mA IOH = 6mA VO = 1V VDD = 3V VDD = 3.3V VO = 1.65V VDD = 3.6V VO = 3.135V VO = 1.95V VDD = 3V VDD = 3.3V VO = 1.65V VO = 0.4V VDD = 3.6V Min. VDD - 0.2 2.1 2.4 Typ.(1) Max Unit V 0.2 0.8 0.55 -28 -36 -14 28 36 14 mA mA
VOL
LOW level Output Voltage
V
IOH
HIGH level Output Current
IOL
LOW level Output Current
NOTE: 1. All typical values are at respective nominal VDD.
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IDT5V2305 2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS - VDD = 2.5V 0.2V
Symbol VOH VOL Parameter HIGH level Output Voltage LOW level Output Voltage Test Conditions VDD = Min. to Max. IOH = -100A VDD = 2.3V IOH = -6mA VDD = Min. to Max. IOH = 100A VDD = 2.3V IOH = 6mA VO = 1V VDD = 2.3V VDD = 2.5V VO = 1.25V VDD = 2.7V VO = 2.375V VO = 1.2V VDD = 2.3V VDD = 2.5V VO = 1.25V VO = 0.3V VDD = 2.7V Min. VDD - 0.2 1.8 Typ.(1) Max Unit V V
0.2 0.55 -17 -25 -10 17 25 10
IOH
HIGH level Output Current
mA
IOL
LOW level Output Current
mA
NOTE: 1. All typical values are at respective nominal VDD.
TIMING REQUIREMENTS OVER RECOMMENDED RANGE
Symbol fCLK Parameter Clock Frequency Test Conditions VDD = 3V to 3.6V VDD = 2.3V to 2.7V Min. 0 0 Typ. Max 200 170 Unit MHz
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IDT5V2305 2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE VDD = 3.3V 0.3V(1)
Symbol tPLH tPHL tSK(O)(2) tSK(P) tSK(PP) tR tF tSU tH Parameter CLK to Yx Output Skew, Yx to Yx Pulse Skew Part-to-Part Skew Rise Time Fall Time G before CLK G after CLK Test Conditions f = 0MHz to 200MHz, CL = 25pF Min. 1.3 Typ.(1) Max 2.6 50 300 500 2 2 Unit ns ps ps ps V/ns V/ns ns
VO = 0.4V to 2V VO = 2V to 0.4V V(THRESHOLD) = VDD/2
0.7 0.7 0.1 0.4
NOTES: 1. All typical values are at respective nominal VDD. 2. This specification is only valid for equal loading of all outputs.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE VDD = 2.5V 0.2V(1)
Symbol tPLH tPHL tSK(O)(2) tSK(P) tSK(PP) tR tF tSU tH Parameter CLK to Yx Output Skew, Yx to Yx Pulse Skew Part-to-Part Skew Rise Time Fall Time G before CLK G after CLK Test Conditions f = 0MHz to 170MHz, CL = 25pF Min. 1.5 Typ.(1) Max 3.5 75 700 600 1.4 1.4 Unit ns ps ps ps V/ns V/ns ns
VO = 0.4V to 1.7V VO = 1.7V to 0.4V V(THRESHOLD) = VDD/2
0.4 0.4 0.1 0.4
NOTES: 1. All typical values are at respective nominal VDD. 2. This specification is only valid for equal loading of all outputs.
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IDT5V2305 2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER
INDUSTRIAL TEMPERATURE RANGE
OUTPUT ENABLE GLITCH SUPPRESSION CIRCUIT
The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the clock input such that the output buffer will be enabled on the next full period of the input clock (negative edge triggered by the input clock). The G input must be stable one tEN - time prior to the falling edge of the CLK for predictable operation.
CLK
Gx tEN tDIS
Yx
G (tEN, tDIS) Relative to CLK
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IDT5V2305 2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
FROM OUTPUT UNDER TEST
CL
500
NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 200MHz; ZO = 50; tR < 1.2ns; tF < 1.2ns.
Test Load Circuit
VDD CLK tPLH tPHL VOH 1.7V or 2V Yx 0.4V tR tF 0.4V 50% VDD VOL 50% VDD 0V
Voltage Waveforms Propagation Delay Times
VDD CLK 0V VOH Any Y 50% VDD VOL VOH Any Y 50% VDD VOL tSK(O) tSK(O)
Output Skew
VDD CLK 50% VDD 0V tPLH Yx 50% VDD VOL tPHL VOH
tSK(P) =
tPLH
tPHL
Pulse Skew 7
IDT5V2305 2.5V TO 3.3V HIGH PERFORMANCE CLOCK BUFFER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XXXXX Device Type XX Package X Package
I
-40C to +85C (Industrial)
PG NR
Thin Shrink Small Outline Package Thermally Enhanced Plastic Very Fine Pitch Quad Flat No Lead Package 2.5V to 3.3V High Performance Clock Buffer
5V2305
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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